//------------------------------------------------------------
//  Filename: video_enhance.v
//   
//  Author  : wlduan@gmail.com
//  Revise  : 2017-06-08 14:02
//  Description: 
//   
//  Copyright (C) 2014, YRBD, Inc. 					      
//  All Rights Reserved.                                       
//-------------------------------------------------------------
//
`timescale 1ns/1ps
 
module VIDEO_ENHANCE ( 
    input  wire        clk_100mhz,
    input  wire        rst,

    input  wire [15:0] x_org_cnt,
    input  wire [15:0] y_org_cnt,
    input  wire [23:0] dsp_ctrl,
    input  wire [7:0]  pix_black,
    // User fifo in
    input  wire        sensor_wr_en,
    input  wire [32:0] sensor_din,

    // User fifo out
    output reg         camera_wr_en,
    output reg  [32:0] camera_din  ,  

    // User fifo out
    output reg         coproc_wr_en,
    output reg  [32:0] coproc_din    
);  
//--------------------------------------------------------
wire       filter_en  = dsp_ctrl[23];
//--------------------------------------------------------
wire[32:0] filter_din   ;
wire       filter_wr_en ;
//--------------------------------------------------------
VIDEO_FILTER VIDEO_FILTER_inst0( 
    .clk_100mhz     ( clk_100mhz       ) ,
    .rst            ( rst              ) ,

    .x_org_cnt      ( x_org_cnt        ) ,
    .y_org_cnt      ( y_org_cnt        ) ,  
    
    .filter_en      ( filter_en        ) ,
    .pix_black      ( pix_black        ) ,

    .sensor_wr_en   ( sensor_wr_en     ) ,
    .sensor_din     ( sensor_din       ) ,
    
    .camera_wr_en   ( filter_wr_en     ) ,
    .camera_din     ( filter_din       )
); 
//--------------------------------------------------------
wire   clk = clk_100mhz;
//--------------------------------------------------------
always @(posedge clk,posedge rst) begin
    if(rst)begin 
        camera_din   <= 33'b0; 
        camera_wr_en <= 1'b0;   
    end 
    else begin 
        camera_din   <= filter_din; 
        camera_wr_en <= filter_wr_en;   
    end 
end 
//--------------------------------------------------------
always @(posedge clk,posedge rst) begin
    if(rst)begin 
        coproc_din   <= 33'b0; 
        coproc_wr_en <= 1'b0;   
    end 
    else begin 
        coproc_din   <= filter_din; 
        coproc_wr_en <= filter_wr_en;   
    end 
end 
//--------------------------------------------------------
// To be Done
//


endmodule

